Microvias, HDI stackups and what they cost, written for the person routing the board
Cross sections, design rules and real capability limits for 1+N+1 through any-layer construction. Everything on one page, no marketing decks.
01 The anatomy of an HDI stackup
Read it from the middle out: a cured core, then one build-up layer at a time pressed onto each side.
Short answer. An HDI stackup is a conventional laminated core with one or more sequentially laminated build-up layers on each side, joined by laser drilled microvias instead of through holes. Choose the build by counting how many signal rows must escape the tightest BGA: one row per laser layer is the planning number, two if you allow via in pad and fine lines.
In the centre sits the core, a fully cured piece of laminate with copper on both faces, often carrying buried vias drilled and plated before anything else happens. Outwards from there, each build-up layer is a sheet of prepreg plus copper foil pressed onto what came before, then laser drilled, desmeared and plated. The notation 2+N+2 reads exactly that way: two build-up layers, an N layer core, two build-up layers.
Two details cause most of the back and forth with a fabricator. The outer dielectrics have to be thin single ply prepreg, because a laser must get through in one pass without damaging the target pad. And the buried via crosses only the core, so it is drilled and filled long before the outer layers exist.
Choosing layer count and build type
Start from the package, not the layer count. Count the rows of balls that must reach a plane or a trace, subtract the rows you can dog-bone on the surface, and that is roughly how many laser layers you need.
| BGA pitch | Typical I/O | Build that works | Rows escaped | Typical layers |
|---|---|---|---|---|
| 0.8 mm | < 400 | Through hole, no HDI | 2–3 | 4–8 |
| 0.65 mm | 400–700 | 1+N+1 | 3–4 | 6–8 |
| 0.5 mm | 500–1200 | 1+N+1 or 2+N+2 | 4–6 | 8–12 |
| 0.4 mm | 800–1700 | 2+N+2 | 6–8 | 10–14 |
| 0.4 mm, high I/O | > 1700 | 3+N+3 | 8–10 | 12–18 |
| 0.35 mm and finer | any | ELIC / any-layer | unlimited | 8–16 |
Dielectric and material selection
Laser drilling is a thermal process and glass does not ablate the way resin does. That is why build-up layers use open weave, low glass styles, and why resin coated copper shows up on the finest builds. A heavy 7628 prepreg on a laser layer gives ragged holes and inconsistent depth.
| Prepreg style | Pressed thickness | Resin content | Where it belongs |
|---|---|---|---|
| 106 | 50–60 µm | 72–75 % | Thin outer laser layer, fine microvias |
| 1080 | 70–85 µm | 62–68 % | Default build-up dielectric |
| 2116 | 105–120 µm | 54–57 % | Inner build-up, impedance layers |
| 7628 | 175–195 µm | 44–48 % | Core and non-laser layers only |
| RCC / resin film | 40–70 µm | glass free | Any-layer and fine pitch build-ups |
Mid Tg FR-4 at 150–170 °C covers most commercial work. Move to high Tg or a low loss system when the board sees more than three lamination cycles, lead free reflow more than twice, or signal edges fast enough that Df matters. To sanity check a proposed material set against what a shop can actually press, a fabricator's published HDI PCB Stackup capability page is a faster read than a laminate datasheet, because it shows the combinations already running in production.
Impedance on build-up layers
HDI does not change the impedance maths, it changes which layers you may use. Outer build-up signal layers sit very close to their reference plane, so a 50 Ω single ended trace over a 76 µm dielectric lands near 3.5 mil wide instead of the 5 to 6 mil of a conventional board.
- Give every build-up signal layer an adjacent solid plane. On a 2+N+2 that usually means L2 and L7 are ground.
- Never reference a signal across a split on a build-up layer; there is no room for a stitching via to fix it.
- Plated outer copper finishes near 35–45 µm after fill plating, which widens the trace bottom and drops impedance.
- Ask for a coupon impedance report, not a calculation.
02 Four builds, drawn to the same scale
Every extra laser layer is another full lamination cycle. That is where both the routing density and the price come from.
| Build | Layers | Laser layers | Lamination cycles | Min BGA pitch | Relative cost | Where it is used |
|---|---|---|---|---|---|---|
| 1+N+1 | 4–10 | 1 per side | 1 | 0.5–0.65 mm | 1.3–1.6× | Fan-out for mid pitch BGAs, cost sensitive products |
| 2+N+2 | 8–16 | 2 per side | 2 | 0.4–0.5 mm | 1.8–2.4× | Dense SoC and FPGA boards, industrial modules |
| 3+N+3 | 10–20 | 3 per side | 3 | 0.35–0.4 mm | 2.4–3.2× | High I/O processors, backplane line cards |
| ELIC / any-layer | 6–16 | every layer | n−1 | 0.3 mm and finer | 3–4.5× | Handsets, wearables, area constrained modules |
03 Microvia rules that survive DFM and reflow
Diameter, depth, pads and fill. The numbers a fabricator checks before they quote.
Short answer. Draw microvias at 100 µm entry diameter into a 75 µm dielectric, with a 250 µm capture pad and a target pad at least 100 µm larger than the hole bottom. Keep aspect ratio at or below 0.8:1, copper fill anything stacked or sitting in a pad, and limit stacks to two levels unless the fabricator has reliability data for more.
The target pad is the one that causes trouble. Laser registration drifts with every lamination cycle, so a pad sized exactly to the hole bottom on layer three can end up with the via landing off centre after the third press.
- No teardrops on microvias; they do nothing for a laser hole.
- Keep 75 µm clearance from a capture pad to an adjacent plane edge.
- A microvia in a BGA pad uses that pad as its capture pad, filled and planarised.
- Leave non functional pads on the target pads of stacked vias — that is structural, not electrical.
| Parameter | Standard | Advanced | Limit |
|---|---|---|---|
| Laser entry diameter | 100 µm | 75 µm | 60 µm |
| Dielectric thickness, one laser layer | 75–80 µm | 60 µm | 40 µm |
| Aspect ratio, depth : entry diameter | 0.75 : 1 | 0.9 : 1 | 1 : 1 |
| Capture pad diameter | 250 µm | 200 µm | 175 µm |
| Target pad diameter | 250 µm | 200 µm | 175 µm |
| Line / space, build-up layers | 75 / 75 µm | 50 / 50 µm | 40 / 40 µm |
| Via to via pitch | 400 µm | 300 µm | 250 µm |
| Copper fill dimple | ≤ 10 µm | ≤ 7 µm | ≤ 5 µm |
Five lines worth writing into the fab note
- Copper fill with a dimple no greater than 10 µm on every stacked via.
- Microvia target pads shall not be reduced below the design value during production optimisation.
- Microstructure evaluation per IPC-6012 on the first article, including a cross section through a stacked via.
- Interconnect stress testing on the coupon for builds with three or more stacked levels.
- No microvia landing directly on an unfilled through hole barrel.
Those five cost nothing at design time and settle most of the arguments that otherwise happen after the first thermal cycle batch. When the design moves from rules to a real build, read a fabricator's published capability for Microvia PCB work, since the stack depth, fill dimple and minimum laser diameter they hold in production are the real limits your drawing has to live inside.
04 Stacked or staggered
Same three dielectrics, two ways to cross them, very different reliability conversations.
A stacked structure transfers z-axis expansion straight through a column of fill copper. If the fill has a void, or the dimple on the lower via is deep enough that the upper via sits in a cup rather than on a plane, the strain lands on a small annulus at the target pad interface. That is the crack location in most failure analyses, and why IPC-6012 Amendment 1 tightened the requirements for these structures.
None of that makes stacking wrong. It makes fill process control part of your specification rather than the fabricator's private business.
- Under the BGA field, stack. There is no room to do anything else.
- Outside the BGA field, stagger. The routing channel exists out there.
- If a stack must be three deep, break it: two stacked, one staggered step, then continue.
- Automotive, medical, long service life: stagger by default and justify every stack.
| Stacked | Staggered | |
|---|---|---|
| Routing area used | One pad footprint | Two to three pad footprints per level |
| Fill requirement | Copper fill mandatory | Resin fill or unfilled acceptable |
| Relative cost per laser layer | +10–20 % | baseline |
| Thermal cycle robustness | Sensitive to fill quality at the interface | More forgiving |
| Via in pad compatible | Yes, planarised | First level only |
| Typical use | 0.4 mm pitch BGA, any-layer builds | General HDI, automotive and industrial |
05 What sequential lamination actually does
Six process steps per side, per build-up layer, on top of the core work.
This is the honest reason HDI costs more, and also why yield falls as laser layers stack up: registration error accumulates with every press cycle. It is why a design that closes its escape on one laser layer is worth real money compared with one that needs two.
A worked 8 layer example
A 0.4 mm pitch, 900 ball SoC on a 1.6 mm board. Six rows must escape. Two laser layers per side give four rows on the build-up layers, two more escape on the core layers through the buried via, and the rest are power and ground dropping straight onto planes.
| Layer | Function | Copper | Dielectric below | Via access |
|---|---|---|---|---|
| L1 | Signal, BGA field | 35 µm | 1080, 76 µm | Microvia to L2, filled |
| L2 | Ground | 18 µm | 1080, 76 µm | Microvia to L3, stacked |
| L3 | Signal, escape | 18 µm | 2116, 110 µm | — |
| L4 | Power | 35 µm | core 0.4 mm | Buried via to L5 |
| L5 | Power | 35 µm | 2116, 110 µm | — |
| L6 | Signal, escape | 18 µm | 1080, 76 µm | Microvia to L7 |
| L7 | Ground | 18 µm | 1080, 76 µm | Microvia to L8 |
| L8 | Signal, bottom | 35 µm | — | — |
Finished thickness lands at 1.55 mm before mask, inside a ±10 % tolerance on 1.6 mm. Through holes still exist for the connectors, drilled 0.25 mm after the last press.
06 HDI cost estimator
Put numbers against a build before you commit. Same drivers a fabricator uses: area, layers, laser layers, line width, fill, finish.
What moves the price
| Driver | Effect on panel price | What you can do about it |
|---|---|---|
| Sequential laminations | +15–30 % each | Close the escape on fewer laser layers; use buried vias in the core |
| Panel utilisation | up to −40 % | Adjust outline or array step to fit one more row per panel |
| Line and space below 75 µm | +8–45 % | Apply fine geometry only on the layers that need it |
| Copper fill | +12–20 % | Fill only stacked vias and vias in pads |
| Material class | +10–160 % | Match Tg and loss to the real thermal and signal budget |
| Lead time | +15–60 % | Book panel time early rather than paying expedite |
07 Capability limits to quote against
Design inside the standard column and DFM comes back quiet.
| Parameter | Standard | Advanced | Limit |
|---|---|---|---|
| Layer count | 4–16 | 18–24 | 32 |
| Build type | 1+N+1, 2+N+2 | 3+N+3 | any-layer |
| Finished thickness | 0.6–2.4 mm | 0.4–3.2 mm | 0.25–4.0 mm |
| Thickness tolerance | ±10 % | ±8 % | ±5 % |
| Laser via diameter | 100 µm | 75 µm | 60 µm |
| Mechanical drill | 0.20 mm | 0.15 mm | 0.10 mm |
| Through hole aspect ratio | 10 : 1 | 14 : 1 | 20 : 1 |
| Line / space, outer | 75 / 75 µm | 50 / 50 µm | 40 / 40 µm |
| Line / space, inner | 65 / 65 µm | 40 / 40 µm | 30 / 30 µm |
| Layer to layer registration | ±50 µm | ±35 µm | ±25 µm |
| Solder mask dam | 100 µm | 75 µm | 60 µm |
| Impedance tolerance | ±10 % | ±7 % | ±5 % |
| Stacked microvia levels | 2 | 3 | 4+ |
| Copper fill dimple | ≤ 10 µm | ≤ 7 µm | ≤ 5 µm |
| Surface finish | ENIG, HASL LF, OSP | ENEPIG, immersion Ag/Sn | hard gold, selective |
| Materials | FR-4 mid/high Tg | halogen free, low Dk/Df | PTFE, hybrid, polyimide |
Different shops draw these lines in different places, particularly on stacked via count and registration. Before finalising a design that lives in the advanced column, confirm the numbers with the fabricator who will build it, and ask what their first pass yield looks like at those values.
08 Questions
Updated 2026-09-19
What is a microvia?
A microvia is a laser drilled hole of 150 µm diameter or less that connects one copper layer to the next through a single dielectric. IPC-2315 allows an aspect ratio of depth to diameter up to 1:1; production shops design to 0.8:1. Microvias are what let a 0.4 mm pitch BGA escape without through holes eating the routing channels.
When do I actually need HDI?
Three triggers: BGA pitch of 0.5 mm or finer, more than about six signal rows under a package, or a board that has run out of routing room at 4 mil line and space. Below those, a conventional through hole build is cheaper and faster.
What is the maximum microvia aspect ratio?
IPC-2315 allows 1:1 depth to diameter. Most shops hold 0.75:1 to 0.8:1, because the plating chemistry has to reach the bottom of the hole and fill it without voids. For a 75 µm dielectric that means a 100 µm laser hole.
Do microvias need to be filled?
Only when they are stacked, when they sit inside a surface mount pad, or when the pad has to be flat for a fine pitch part. A single staggered microvia landing on a normal pad can be resin filled or left unfilled, which is cheaper.
How many microvias can I stack?
Two is routine. Three is common in 3+N+3 and any-layer builds but should come with fill process control and coupon testing. Four or more is rare outside handset production and needs a fabricator who can show reliability data.
Does an HDI stackup have to be symmetric?
For warp control, yes. Keep copper distribution, dielectric thickness and laser layer count mirrored about the centre of the board. Asymmetric builds can be made, but expect a bow and twist waiver above 0.75 %.
What files does a fabricator need?
Gerber X2 or ODB++, an NC drill file with every via span separated and named, a stackup drawing with dielectric thickness and impedance targets, a fab note covering fill and finish, and an IPC netlist. Separating the drill spans is the one people forget, and it stops a quote dead.
How long does an HDI prototype take?
A 1+N+1 prototype runs 7–10 working days, 2+N+2 around 10–14, and 3+N+3 or any-layer 15–20. Each lamination cycle is a real day in the factory, not a scheduling buffer.
Does HDI improve signal integrity?
Usually yes. Microvias have far less stub and inductance than a through hole, and thin build-up dielectrics let you keep tight coupling to a nearby reference plane. On multi-gigabit links, removing through hole stubs is often worth more than the routing density.
How much more does an HDI board cost?
Each sequential lamination adds roughly 15–30 % to the bare board price. A 1+N+1 build is typically 1.3–1.6× an equivalent through hole board; a 3+N+3 or any-layer build can be 2.5–4×. The estimator on this page puts numbers against your own build.
09 Talk to an engineer
Send a stackup, a drill table or a photo of a cross section. Replies come from someone who has built the construction you are asking about.
Fastest route
WhatsApp, with layer count, tightest BGA pitch, board size and quantity in the first message. That is usually enough for an answer without a call.
engineering@microviapcb.com
Gerbers, ODB++ or a stackup PDF, up to 25 MB.
Hours
09:00–19:00 GMT+8, Monday to Saturday. Messages outside those hours are answered the next working morning.
Quotation and fabrication
Pricing, DFM and production run through PCBSync, which quotes HDI builds from 1+N+1 to any-layer.
What to send for a quote
| Item | Why it matters |
|---|---|
| Gerber X2 or ODB++ | Layer order and net data in one package |
| Drill file with separated spans | Tells the fab which vias are laser and which are mechanical |
| Stackup drawing | Dielectric thickness, copper weight, impedance targets |
| Board size and quantity | Panel utilisation drives most of the price |
| Material and finish | Tg, loss class, ENIG or ENEPIG |
| Lead time needed | Expedite is priced per lamination cycle |
No files yet? Send the layer count and BGA pitch. That is enough to come back with a build proposal and a budget number.